In conventional gate first CMOS integration flow, a self aligned silicide process is used to form low resistivity contacts on the source/drain and gate electrodes after the gate stack is formed. This is typically implemented by reacting a metal, such as nickel (Ni), e.g., a nickel (Ni)/platinum (Pt) alloy with silicon (Si) on an exposed surface containing Si.
Metal gate electrodes have evolved for improving CMOS drive current by reducing polysilicon depletion that occurs with polysilicon gate electrodes. However, simply replacing polysilicon gate electrodes with metal gate electrodes engenders issues in forming the metal gate electrode prior to high temperature annealing to activate the source/drain implants, as at a temperature in excess of 900° C. Such elevated temperatures tend to degrade the metal gate electrode or cause interaction with the gate dielectric, thereby adversely impacting transistor performance. Gate last high-K metal gate, also called replacement gate, techniques have been developed to address problems attendant upon substituting metal gate electrodes for polysilicon gate electrodes. For example, an amorphous silicon (a-Si) or polysilicon gate is used during initial processing until high temperature annealing to activate source/drain implants has been implemented. Subsequently, the a-Si or polysilicon is removed and replaced with a metal gate.
The migration to gate last high-K/metal gate integration has engendered problems with the thermal stability and resistivity of Ni/Pt silicide films due to the high temperature thermal cycles to which they are subjected during deposition of the high-K dielectric and replacement gate metal fill. The exposure to high temperatures post silicidation causes physical and morphological changes in the silicide film, thereby degrading electrical properties. Consequently, MOSFET device performance is adversely impacted due to poor series resistance and channel strain degradation.
A need therefore exists for methodology enabling the formation of low resistivity self aligned silicide contacts with a replacement gate process, and the resulting devices.